Verification Engineer Platforms Team
Codasip · Bristol
Codasip designs RISC-V processor cores and systems with security built in at the hardware level, from design centres including Bristol and Cambridge. This senior verification engineer in the Platforms team checks new Codasip IP for secure systems, at both IP and system level.
Apply on Codasip- Company
- Codasip
- Where
- Bristol
- Function
- Engineering
- Posted
- 2 days ago
- Team
- Platforms
- Seniority
- Senior
- Work mode
- On-site
The role
What you’ll do
- Turn architecture specs into verification plans, test scenarios and coverage goals
- Build reusable SystemVerilog and UVM testbenches, including formal setups
- Run simulations, debug failures and close coverage gaps, with FPGA validation support
- Work with hardware and software engineers and report on progress and risk
What you’ll need
- Hands-on IP and system-level verification with SystemVerilog and UVM
- Experience with functional coverage, SVA assertions and formal methods
- Coding and scripting skills in Python, C++ or Rust plus Linux automation
- Good knowledge of processor architecture; AXI, AHB or APB experience helps
Good to know: Open only to candidates already in the UK with the right to work here. Preferably based at the Bristol or Cambridge design centre.
Events for people in this role
Bristol events that suit this role. We haven't seen Codasip confirmed at these.
About Codasip
DeepTech and SaaS. Backed by b2venture, btov Partners, Indaco Venture Partners and Octopus Ventures. Stage: series_unknown.
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