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EngineeringOn-siteMid

Hardware Validation & Debug Engineer - DDR

Graphcore · Bristol

Graphcore, part of SoftBank, builds hardware, systems and software for AI compute. This lab-based role validates the memory and system interfaces on its new boards, with LPDDR5-9600 at the centre, and owns bring-up, root-causing failures and tuning the memory subsystem until it holds up under real product conditions.

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Company
Graphcore
Where
Bristol
Function
Engineering
Posted
6 weeks ago
Team
Hardware Test Engineering
Seniority
Mid
Work mode
On-site

The role

What you’ll do

  • Write and run validation and debug plans for new hardware platforms
  • Lead board bring-up and chase failures through to root cause
  • Tune LPDDR memory subsystems, including training, timing and margins
  • Report findings clearly and turn them into actions for hardware and firmware teams

What you’ll need

  • Strong hands-on hardware debug, including board bring-up and subsystem debug
  • Experience validating and tuning LPDDR memory, ideally LPDDR5
  • Knowledge of DDR training, margin analysis, eye diagrams and stability testing
  • Confidence with high-bandwidth scopes, BERT systems and VNA or TDR kit

Good to know: No visa sponsorship; existing UK right to work needed. Flexible working, up to 5% matched pension, phantom equity, free food and on-site barista.

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About Graphcore

DeepTech, AI & ML and SaaS. Backed by Balderton Capital, Molten Ventures and Sequoia Capital. Stage: other.

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